Gate dielectric performance and reliability is an ongoing concern in conventional CMOS processing. This concern is particularly significant as device geometries shrink to the sub-micron realm (e.g., 90 nm, 65 nm, and below) and as device reliability standards are strengthened. Two approaches are employed to increase device performance in smaller geometry devices. One approach is to decrease the thickness of the silicon dioxide gate dielectric, which will increase higher gate dielectric leakage current. Another approach is to employ so-called high-k gate dielectrics (i.e., gate dielectrics having a permittivity constant of greater than about 3.9, the permittivity of silicon oxide), which can be considerably thinner equivalent oxide thickness (EOT) than a conventional silicon oxide layer, while providing electrical insulation comparable to a considerably thicker silicon oxide layer. Due to the undesirable interactions between high-k dielectrics and the underlying semiconductor material (usually silicon, germanium, silicon germanium, and the like) to degrade carrier mobility, a thin silicon oxide layer is typically employed as part of the gate dielectric even when a high-k gate dielectric is employed.
Well known phenomena of the silicon oxide gate dielectric that can deleteriously affect device performance include charge traps such as intrinsic and extrinsic defects throughout the oxide layer, and so-called interface states at the oxide-silicon interface resulting from silicon dangling bonds. Additionally, charge trapping sites are also known to form at the interface between a nitrogen containing dielectric and a non-nitrogen containing dielectric layer, such as may be employed in the case of a silicon oxide and high-k composite gate dielectric.
It is known that the introduction of nitrogen into the silicon oxide dielectric layer, a process known as nitridation (by thermal process, or plasma process), can eliminate some of the charge trapping sites that otherwise exist. A nitrided oxide layer (or any nitrogen containing dielectric), however, may have other deleterious affects on the underlying substrate, such as nitrogen diffusion into the substrate, and poor device characteristics due to nitrogen-incorporated dopant diffusion or dopant deactivation in a source/drain and their extensions.
Particularly, negative bias temperature instability (NBTI) may be adversely impacted by the presence of a nitrogen containing material in contact with the substrate (and more particularly in contact with the channel region). While the beneficial affects of a nitrided gate electrode (such as reduced charge trap sites) may outweigh the negative effects for some transistor applications, such as core logic devices, the deleterious effects are more significant for other applications such as input/output (I/O) devices. This is because I/O transistors typically operate at higher voltages (e.g., 5V, 3.3V, 2.5V, 1.8V, or another relatively higher bias (dependent on using which technology)) than core logic and memory devices, which may operate at a voltage at a lower bias (e.g., in the 1.5, 1.2, or 1V range).
What is needed, therefore, is to find a device and manufacturing method that provides the advantageous features of a nitrided dielectric layer and a high-k dielectric layer, which will increase device and circuit performance for both peripheral (or I/O) and core devices, but not degrade or negatively impact their reliabilities.